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Friday, November 4 • 12:00pm - 12:45pm
Dealing with Register Hierarchies

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Many architectures allow addressing parts of a register independently. Be it 
the infamous high/low 8 bit registers of X86, the 32/64bit addressing modes of 
X86-64 and AArch64 or GPUs with wide loads and stores where with computation on 
sub register lanes. 

LLVM recently gained support to track liveness on subregister granularity. In 
combination with improved heuristics for register classes of varying sizes the 
average register count decreased for 20% for GPU shader programs. 

This talk gives an introduction to typical situations benefiting from sub 
register liveness modeling. It shows how a target architecture developer can 
model them and explains the register allocation techniques employed by llvm.

avatar for Matthias Braun

Matthias Braun

Apple Inc.
I am an LLVM developer working on the code generation part of the compiler, specifically register allocation and scheduling.

Friday November 4, 2016 12:00pm - 12:45pm PDT
1 - General Session (Rm LL20ABC)