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Thursday, November 3 • 5:00pm - 5:45pm
Representing composite SIMD operations in LLVM-IR

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Loop Vectorizer currently translates scalar operations into a new sequence of SIMD operations where every operation can be represented very naturally in LLVM-IR using its native instructions and vector operands. This sequence passes though common and target-specific optimizations before being lowered to target code. 
However, we aim to work with composite operations or idioms during vectorization. This requirement stems from the rich vector ISA’s supported by targets – SIMD instruction sets include CISC-like operations such as clamping or saturating arithmetic, multiply-and-accumulate-pairs or sum-of-absolute-differences. Two additional categories of such non-primitive vector operations are nonconsecutive forms of memory accesses and masked vector operations. Current LLVM-IR can support such idioms by patterns of instructions or intrinsics, making cost estimation and/or following optimization steps problematic. 
As a part of our drive to enhance vectorization in LLVM, we are revisiting the ability of LLVM-IR to represent composite SIMD operations. 
In this session we’d like to discuss the different categories of composite SIMD operations, alternative approaches to represent them and propose a new generic solution. 


Thursday November 3, 2016 5:00pm - 5:45pm PDT
3 - BoF (Rm LL21CD)