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Thursday, November 3 • 11:15am - 12:00pm
Scalable Vectorization for LLVM

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SVE is a new vector ISA extension for AArch64 targeted at HPC applications; one major distinguishing feature is that vector registers do not have a fixed size from a compiler perspective. This talk will cover the changes made to LLVM IR to support vectorizing loops in a vector length agnostic manner, as well as improvements in vectorization enabled by the predication and gather/scatter features of the extension. See https://community.arm.com/groups/processors/blog/2016/08/22/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture for more details on the architecture.

Speakers
avatar for Amara Emerson

Amara Emerson

Senior Engineer, ARM
Senior Engineer in the HPC compilers and tools group at ARM. Talk to me about HPC, compiler optimizations, research collaborations, auto-vectorization and ARM SVE.
avatar for Graham Hunter

Graham Hunter

Senior Engineer, ARM
Compiler engineer in ARM's HPC and server tools division. OpenMP language committee member. Talk to me about HPC, compiler optimizations (particularly auto-vectorization), OpenMP, and ARM's SVE.


Thursday November 3, 2016 11:15am - 12:00pm
2 - Technical Talk (Rm LL21AB)

Attendees (32)