SVE is a new vector ISA extension for AArch64 targeted at HPC applications; one major distinguishing feature is that vector registers do not have a fixed size from a compiler perspective. This talk will cover the changes made to LLVM IR to support vectorizing loops in a vector length agnostic manner, as well as improvements in vectorization enabled by the predication and gather/scatter features of the extension. See https://community.arm.com/groups/processors/blog/2016/08/22/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture for more details on the architecture.
Senior Engineer in the HPC compilers and tools group at ARM. Talk to me about HPC, compiler optimizations, research collaborations, auto-vectorization and ARM SVE.
Compiler engineer in ARM's HPC and server tools division. OpenMP language committee member. Talk to me about HPC, compiler optimizations (particularly auto-vectorization), OpenMP, and ARM's SVE.
